FPGA Programming Flashcards

Question 1

What does the acronym FPGA stand for in digital design?

Accepted Answer

FPGA stands for field programmable gate array. It is an integrated circuit containing a grid of configurable logic blocks, programmable interconnects, and input and output blocks. Its function is set by a configuration loaded after manufacture, so the same chip can implement many different digital circuits.

Question 2

What is a lookup table inside an FPGA logic element?

Accepted Answer

A lookup table is a small memory that stores the output value for every combination of its inputs, so it can implement any Boolean function of those inputs. Configuration bits fill the table. Pairing a lookup table with a flip flop lets a logic element store results as well as compute them.

Question 3

What are the main programmable resources found in a typical FPGA?

Accepted Answer

A typical FPGA contains configurable logic blocks for computation, programmable routing that connects them, input and output blocks at the device edge, and embedded resources such as block RAM and digital signal processing slices. Clock management circuits, often phase locked loops, distribute and adjust clock signals.

Question 4

How does an FPGA differ from a microprocessor when running a program?

Accepted Answer

An FPGA does not execute instructions one after another the way a microprocessor does. Instead, the configured circuit performs many operations in parallel, with each piece of hardware dedicated to one task. This gives predictable timing and high throughput, though development requires describing hardware rather than writing sequential software.

Question 5

What is volatile configuration memory, and why does it matter for SRAM based FPGAs?

Accepted Answer

Volatile configuration memory loses its contents when power is removed. SRAM based FPGAs store their configuration in this kind of memory, so the design must be loaded again at every power up from an external flash device or other source. Some other FPGA families use nonvolatile configuration memory, which keeps the design without reloading.

Question 6

What is the difference between combinational and sequential logic in an FPGA design?

Accepted Answer

Combinational logic produces outputs that depend only on current inputs, with no stored state. Sequential logic includes memory elements such as flip flops, so its outputs also depend on earlier values, usually updated on a clock edge. FPGA logic elements provide both, letting designers build pipelines, counters, and state machines.

Question 7

Why do FPGA designers use a global clock network?

Accepted Answer

A global clock network is a dedicated set of low skew wires that delivers a clock signal to registers across the device with nearly equal delay. Designers normally route clocks through these networks rather than through ordinary logic, because logic delays would make timing unreliable.

Question 8

What does a hardware description language let a designer express that ordinary software languages do not?

Accepted Answer

A hardware description language lets a designer describe structure and concurrency directly: which signals connect which blocks, and which operations happen at the same time. Ordinary software languages assume sequential execution, so they hide timing and wiring. HDL code is later synthesized into real logic, not run as a program.

Question 9

What is the difference between a signal and a variable in VHDL?

Accepted Answer

In VHDL, a signal models a wire. Assigning to it schedules a new value that takes effect only after the current process suspends. A variable holds its value immediately and is local to the process where it is declared. Signals model hardware connections, while variables are mainly useful for intermediate calculations.

Question 10

What is the difference between blocking and nonblocking assignments in Verilog?

Accepted Answer

Blocking assignments, written with an equals sign, execute in order, so each one completes before the next statement starts. Nonblocking assignments, written with less than or equal sign, schedule updates that take effect at the end of the time step. Designers usually use nonblocking assignments for sequential logic.

Question 11

Why is a process or always block with an incomplete sensitivity list a common source of bugs?

Accepted Answer

A combinational process with an incomplete sensitivity list may not re-run when an unlisted input changes, so simulation can show outdated values. Synthesis still builds the intended logic, which means the simulated and physical behavior can disagree. Listing every input, or using the Verilog always star form, prevents this problem.

Question 12

What does a testbench do in HDL development?

Accepted Answer

A testbench is a simulation only description that instantiates the design under test, applies input stimulus, and checks outputs against expected results. It does not become hardware and is never synthesized. Writing a testbench lets a designer verify behavior before programming a device.

Question 13

What is the purpose of a component instantiation in VHDL or a module instantiation in Verilog?

Accepted Answer

Instantiation places a copy of a previously written module inside a larger design and connects its ports to signals in the parent. This lets designers build hierarchy, reusing a counter or adder many times without rewriting it. Port maps in VHDL and named port connections in Verilog make each connection explicit.

Question 14

How does a behavioral description differ from a structural description in HDL?

Accepted Answer

A behavioral description states what the circuit should do, using operators, conditionals, and processes, and leaves the gate level details to synthesis. A structural description states how the circuit is built, by connecting named components and signals. Designers mix both styles, using structure for top level wiring and behavior for logic inside each block.

Question 15

Why should a designer avoid latches created by unintended incomplete conditional assignments?

Accepted Answer

An unintended latch appears when a combinational process does not assign an output on every path, so the synthesized circuit must hold the previous value. Latches are timing hazards and are often unwanted in synchronous designs. Assigning default values at the start of the process, or covering every branch, removes the latch.

Question 16

What is a reset signal used for in a synchronous HDL design?

Accepted Answer

A reset signal forces registers to a known starting state, such as all zeros, so the circuit begins operation from a predictable condition. Synchronous resets take effect only on a clock edge, while asynchronous resets act immediately. Choosing between them affects timing analysis and how the reset is routed across the device.

Question 17

What does synthesis do to an HDL description?

Accepted Answer

Synthesis converts an HDL description into a netlist of logic, flip flops, and other primitives. The tool optimizes the logic and maps it onto lookup tables and registers. Place and route then assign these pieces to physical locations. The result is hardware, not a program that runs on a processor.

Question 18

What is a bitstream, and how is it produced?

Accepted Answer

A bitstream is the binary configuration file that sets the lookup tables, routing switches, and other programmable elements of an FPGA. It is produced at the end of the implementation flow, after synthesis, placement, and routing have fixed every resource's location. The file is then loaded into the device through a programming interface.

Question 19

What is a functional simulation, and how does it differ from a timing simulation?

Accepted Answer

A functional simulation checks whether the HDL logic produces correct values, ignoring physical delays. A timing simulation uses delay information from the placed and routed design to check behavior under realistic propagation delays. Functional simulation runs faster and catches logic errors early, while timing simulation reveals problems that appear only with real delays.

Question 20

Why is a simulation alone not enough to verify an FPGA design?

Accepted Answer

Simulation alone is not enough because it checks only the scenarios written into the testbench. It cannot prove correctness for every input sequence, and it does not capture the real device's electrical behavior or environmental effects. Hardware testing on the board, together with timing analysis, confirms the design works in its actual environment.

Question 21

What makes a testbench self checking, and why is that useful?

Accepted Answer

A self checking testbench compares the design's outputs against expected values in its own code and reports mismatches automatically. This removes the need to inspect waveforms by hand for every test. It makes regression testing practical, because the same suite can be rerun after each change and any failure is flagged at once.

Question 22

What is a waveform viewer used for in FPGA development?

Accepted Answer

A waveform viewer displays how signals change over simulation time, letting a designer see the order and timing of events. Engineers use it to check whether a state machine moves through the expected states and whether registers capture data on the correct clock edge. It helps locate the first point where results diverge.

Question 23

What is the purpose of a code coverage report in verification?

Accepted Answer

A coverage report shows which lines, branches, or states of the HDL code were exercised during simulation. Gaps in coverage point to scenarios the testbench never reached, so the designer can add tests for them. Coverage shows what was executed, not whether the outputs were correct.

Question 24

Why do designers often run the same testbench after every change to the design?

Accepted Answer

Running the same tests after each change is called regression testing, and it catches bugs that a modification accidentally introduces into code that previously worked. Because the tests are automated and repeatable, checking each change stays inexpensive, so designers can check often.

Question 25

What is a clock period, and how does it relate to clock frequency?

Accepted Answer

A clock period is the time from one rising edge of a clock to the next, measured in seconds or nanoseconds. Frequency is the reciprocal of the period, so a 10 nanosecond period corresponds to 100 megahertz. A shorter period leaves less time for signals to travel through logic between registers.

Question 26

What is setup time for a flip flop?

Accepted Answer

Setup time is the minimum interval before the active clock edge during which the data input must remain stable. If data changes inside this window, the flip flop may capture an incorrect or metastable value. Static timing analysis checks that the data path delay leaves enough margin to meet setup time.

Question 27

What is hold time, and why can it be violated after a clock edge?

Accepted Answer

Hold time is the minimum interval after the active clock edge during which the data input must stay stable. It can be violated when the clock reaches a register late and new data from upstream logic arrives too quickly. Designers fix hold violations by adding delay to the data path.

Question 28

What is a timing constraint, and who supplies it?

Accepted Answer

A timing constraint is a statement that tells the implementation tools the required clock frequency, input and output delays, or path limits. The designer writes constraints in a constraint file, which the tools use to guide placement and routing and to judge whether timing is met.

Question 29

What is the critical path in a synchronous FPGA design?

Accepted Answer

The critical path is typically the register to register path with the longest delay, including logic and routing. It determines the minimum clock period the design can support, because every other path has more slack. Improving the critical path, such as by pipelining or simplifying logic, usually raises the maximum clock frequency.

Question 30

What does positive slack mean in static timing analysis?

Accepted Answer

Positive slack means a path meets its timing requirement with time to spare, while negative slack means the path is too slow and violates the constraint. Slack equals required time minus arrival time. A design is considered to meet timing only when the worst slack across all analyzed paths is nonnegative.

Question 31

Why can routing delay dominate the total delay of a path in an FPGA?

Accepted Answer

In an FPGA, signals often travel through long programmable routing wires and switches, and these connections can account for a large share of a path's total delay. Placement affects this, because logic that communicates heavily should sit close together. Timing reports after implementation break each path into logic and routing delay.

Question 32

What is a multicycle path, and why must a designer declare it carefully?

Accepted Answer

A multicycle path is a path whose data is intentionally allowed more than one clock cycle to settle before it is used. Declaring one relaxes the default single cycle check for that path. A wrong declaration hides real timing failures because the tools stop checking that path against a single cycle deadline.

Question 33

What is pipelining, and what does it trade off?

Accepted Answer

Pipelining inserts registers into a combinational path, splitting it into stages that each do part of the work. Each stage has less logic delay, so the clock can run faster, and throughput increases because a new input can enter every cycle. The cost is added latency and more flip flops, so results appear later.

Question 34

Why do FPGA designers often use dedicated DSP blocks for multiplication?

Accepted Answer

Dedicated DSP blocks contain hard multiplier and accumulator circuits that run faster and use less area than the same arithmetic built from general logic. Using them frees lookup tables and routing for other functions, which helps when a design has many multiplications. Resource counts are limited, so designers must check them early.

Question 35

Why should an asynchronously applied reset be synchronized to the clock?

Accepted Answer

Releasing an asynchronous reset at an arbitrary moment can violate recovery and removal timing, pushing flip flops into metastability. A reset synchronizer holds the reset asserted asynchronously but releases it synchronously, with the release aligned to the clock edge. This gives every register a clean, timed exit from reset.

Question 36

What is a finite state machine, and how is it usually coded in HDL?

Accepted Answer

A finite state machine is a circuit that moves between a fixed set of states according to its inputs and the current state. In HDL it is usually coded as a state register updated on the clock edge, plus combinational logic that computes the next state and outputs. This split aids readability and verification.

Question 37

Why does the choice of data width affect an FPGA design?

Accepted Answer

Wider data paths use more lookup tables, flip flops, and routing, which can consume resources and reduce achievable clock frequency. Narrower paths save area but may limit precision or range. Designers usually choose the smallest width that meets the functional requirement, then verify it with corner case tests.

Question 38

How can a designer share one arithmetic unit across several operations?

Accepted Answer

Time multiplexing lets one arithmetic unit serve several operations by processing them in different clock cycles, with multiplexers selecting its inputs. This reduces the number of multipliers or adders at the cost of throughput, since each operation waits for its turn. The design needs a control state machine to schedule the sharing correctly.

Question 39

Why is it useful to simulate and implement a design early, before the full system is complete?

Accepted Answer

Early implementation reveals resource limits, clock speed problems, and placement issues while changes are still cheap. A small working block can be checked against its specification, and its timing report shows whether the planned architecture is feasible. Finding these problems late often forces a redesign of many modules at once.

Question 40

What should a designer check first when a finished FPGA design fails on the board but passes simulation?

Accepted Answer

Start by confirming that the bitstream loaded correctly and that the clock source, power supply, and pin assignments match the board schematic. Next, review the timing report for violations and examine any constraints that were not applied. Common causes include mismatched pin locations, missing clock constraints, or reset behavior that simulation never exercised.

FPGA Programming Flashcards

1FPGA architecture fundamentals

2HDL concepts in VHDL and Verilog

3Synthesis, simulation and testing

4Timing and constraints

5Applied design and optimization

Learning Resources