Unit
- Logic blocks: Each FPGA logic block contains look-up tables (LUTs) and flip-flops that can implement any combinational or sequential function. LUTs are small RAM cells that store truth tables for up to six inputs.
- Programmable interconnects: A network of wires and programmable switches connects logic blocks, allowing arbitrary routing. Modern FPGAs use hierarchical routing to balance flexibility and speed.
- I/O blocks: These connect the internal fabric to external pins, supporting multiple voltage standards and signaling types. I/O blocks include configurable delays and termination resistors.
- Block RAM: Dedicated memory arrays (typically 36 Kb each) provide high-speed, dual-port storage without consuming logic resources. They can be configured as FIFOs or ROMs.
- DSP slices: Hardened arithmetic units optimized for multiply-accumulate operations, essential for signal processing. They support 18x18 or 27x27 multipliers with cascading.
- Configuration memory: SRAM cells store the bitstream that defines the logic function and routing. The configuration is loaded at power-up from an external flash device.
- Reconfigurability advantage: FPGAs can be reprogrammed in-system to update functionality, fix bugs, or adapt to changing requirements, unlike fixed ASICs.
- Clock management: Phase-locked loops (PLLs) and clock managers generate multiple frequencies with low jitter, distributing clocks across dedicated global networks.
- Power management: Modern FPGAs offer dynamic power scaling through clock gating, voltage islands, and selective block enablement. Designers can deactivate unused resources to reduce static and dynamic power consumption, critical for battery-powered and thermal-constrained applications.
- Partial reconfiguration: This advanced feature allows specific regions of an FPGA to be reprogrammed while other regions continue operating. It enables runtime updates, fault tolerance, and time-multiplexing of hardware functions without interrupting system operation.
- Security features: FPGAs include bitstream encryption, authentication, and anti-tamper mechanisms to protect intellectual property. Some devices integrate physically unclonable functions (PUFs) and secure boot flows to prevent unauthorized cloning or reverse engineering.
System Architecture
Pattern: Island-Style FPGA Architecture
Components:
- Configurable Logic Block (CLB): Contains LUTs, flip-flops, and fast carry logic for arithmetic.
- Switch Matrix: Connects CLBs to horizontal and vertical routing channels.
- Block RAM Columns: Embedded memory banks distributed across the chip.
- DSP Columns: Fixed-function multipliers and adders for digital signal processing.
- I/O Tiles: Programmable IO buffers with configurable drive strength and slew rate.
Code Example
Verilog
module and_gate(input wire a, b, output wire y);
assign y = a & b;
endmoduleA simple AND gate in Verilog. Synthesis tools map this logic to a LUT within a logic block. The assign statement describes combinational logic that is inferred from the expression.
Quick Revision
- FPGA logic blocks contain LUTs and flip-flops for implementing digital functions.
- Programmable interconnects route signals between logic blocks via switch matrices.
- Dedicated hard blocks like BRAM and DSP slices improve performance and density.
- FPGAs are reconfigurable via SRAM-based configuration memory loaded at power-up.